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1

FPGA implementation of high-performance, resource-efficient Radix-16 CORDIC rotator based FFT algorithm

Changela, Ankur, Zaveri, Mazad, Verma, Deepak

Journal:

Integration, the VLSI Journal

Year:

2020

File:

PDF, 1.93 MB

2020

2

[IEEE 2016 20th International Symposium on VLSI Design and Test (VDAT) - Guwahati, India (2016.5.24-2016.5.27)] 2016 20th International Symposium on VLSI Design and Test (VDAT) - A low-power high-speed hybrid full adder

Mewada, Manan, Zaveri, Mazad

Year:

2016

Language:

english

File:

PDF, 134 KB

english, 2016

3

[IEEE 2018 International Conference on Current Trends towards Converging Technologies (ICCTCT) - Coimbatore, India (2018.3.1-2018.3.3)] 2018 International Conference on Current Trends towards Converging Technologies (ICCTCT) - FPGA Implementation of Asynchronous Mousetrap Pipelined Radix-2 CORDIC Algorithm

Changela, Ankur, Zaveri, Mazad, Lakhlani, Anurag

Year:

2018

Language:

english

File:

PDF, 2.68 MB

english, 2018

4

[IEEE 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) - Bangalore, India (2018.9.19-2018.9.22)] 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) - ASIC Implementation of High Performance Radix-8 CORDIC Algorithm

Changela, Ankur, Zaveri, Mazad, Lakhlani, Anurag

Year:

2018

Language:

english

File:

PDF, 1.93 MB

english, 2018

5

[IEEE 2009 NORCHIP - Trondheim, Norway (2009.11.16-2009.11.17)] 2009 NORCHIP - Prospects for building cortex-scale CMOL/CMOS circuits: A design space exploration

Hammerstrom, Dan, Zaveri, Mazad S.

Year:

2009

Language:

english

File:

PDF, 414 KB

english, 2009

6

[IEEE 2016 International Conference on Advances in Computing, Communications and Informatics (ICACCI) - Jaipur, India (2016.9.21-2016.9.24)] 2016 International Conference on Advances in Computing, Communications and Informatics (ICACCI) - An input test pattern for characterization of a full-adder and n-bit ripple carry adder

Mewada, Manan, Zaveri, Mazad

Year:

2016

Language:

english

File:

PDF, 117 KB

english, 2016

7

[IEEE 2012 Nirma University International Conference on Engineering (NUiCONE) - Ahmedabad, Gujarat, India (2012.12.6-2012.12.8)] 2012 Nirma University International Conference on Engineering (NUiCONE) - Analysis of increased parallelism in FPGA implementation of neural networks for environment/noise classification and removal

Ambasana, Nikita B., Zaveri, Mazad

Year:

2012

Language:

english

File:

PDF, 667 KB

english, 2012

8

Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures

Mewada, Manan, Zaveri, Mazad, Thakker, Rajesh

Journal:

Integration, the VLSI Journal

Year:

2019

Language:

english

File:

PDF, 4.70 MB

english, 2019

9

Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures

Mewada, Manan, Zaveri, Mazad, Thakker, Rajesh

Journal:

Integration, the VLSI Journal

Year:

2019

File:

PDF, 4.70 MB

2019

10

Performance/price estimates for cortex-scale hardware: A design space exploration

Mazad S. Zaveri, Dan Hammerstrom

Journal:

Neural Networks

Year:

2011

Language:

english

File:

PDF, 1.20 MB

english, 2011

11

[IEEE 2008 IEEE International Joint Conference on Neural Networks (IJCNN 2008 - Hong Kong) - Hong Kong, China (2008.06.1-2008.06.8)] 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence) - CMOS / CMOL architectures for spiking cortical column

Changjian Gao,, Zaveri, Mazad S., Hammerstrom, Dan

Year:

2008

File:

PDF, 337 KB

2008

12

Transmission Gate and Hybrid Cmos Full Adder Characterization and Power-Delay Product Estimation Based on Mathematical Model

Mewada, Manan, Zaveri, Mazad, Gandhi, Ratnik, Thakker, Rajesh

Journal:

Procedia Computer Science

Year:

2020

File:

PDF, 501 KB

2020

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